AI Engineer – Technical Leader

**Job Details:** ================ **Job Description:** -------------------- **Role Overview** We are seeking a highly experienced **AI Technical Leader** to drive the design and deployment of **next-generation agentic AI systems optimized for FPGA/ASIC platforms**. This role sits at the convergence of: * Large Language Models (LLMs) * Agentic AI & autonomous systems * Retrieval-Augmented Generation (RAG) * Hardware-aware AI system design (FPGA / ASIC / EDA) You will define system architecture, lead technical strategy, and deliver scalable AI solutions that tightly integrate **software intelligence with hardware acceleration**, with a strong focus on **AI model optimization and deployment on FPGA**. **Key Responsibilities** **AI Architecture & System Design** * Architect and implement **end-to-end agentic AI systems** (data → reasoning → action) * Design scalable **multi-agent orchestration frameworks** * Build enterprise-grade **RAG pipelines** for knowledge integration and retrieval * Define system-level architecture bridging cloud, edge, and hardware acceleration **Agentic AI & LLM Development** * Develop advanced agent workflows, including: * Tool-using agents * Planning and reasoning agents * Multi-agent collaboration systems * Evaluate and integrate **state-of-the-art LLMs** (open-source and proprietary) * Optimize **prompting, memory, and reasoning strategies** for performance and reliability **AI Model Optimization on FPGA (Core Focus)** * Lead **AI model optimization and deployment on FPGA platforms**, including: * Quantization (INT8 / BF16 / mixed precision) * Graph compilation and operator fusion * Model partitioning across CPU/GPU/FPGA * Memory and bandwidth optimization * Develop workflows to **map AI models (e.g., CV, LLM inference) from PyTorch/Hugging Face to FPGA** * Enable **low-latency, high-efficiency inference pipelines** on FPGA-based systems * Collaborate with hardware teams to align **model architecture with FPGA constraints (DSP, BRAM, interconnect)** **Hardware-Aware AI Co-Design** * Co-design AI systems with: * FPGA acceleration * ASIC platforms * Heterogeneous compute architectures (CPU/GPU/FPGA) * Integrate AI workflows into **EDA toolchains and hardware design flows** * Drive innovations in **software-hardware co-optimization** **Framework & Platform Development** * Build internal AI platforms leveraging: * LangChain * LlamaIndex * Custom agent orchestration frameworks​ * Develop reusable components for: * Memory management * Tool integration * Knowledge retrieval and indexing​ * Enable scalable deployment pipelines for AI applications on FPGA **Technical Leadership** * Lead architecture design reviews and set technical direction * Mentor senior engineers and guide cross-functional teams * Drive innovation at the intersection of **AI systems and semiconductor platforms** **What Makes This Role Unique** * Define **agentic AI architecture for hardware-native AI systems** * Work at the frontier of: * AI reasoning systems * FPGA-based acceleration * Next-generation computing platforms ​ * High-impact role shaping **AI + semiconductor convergence** **Impact** You will enable a new class of intelligent systems where AI agents are tightly coupled with hardware, delivering: * Real-time decision-making pipelines * Efficient, scalable AI deployment on FPGA * End-to-end automation from model to hardware execution **Summary** This role is ideal for a senior technical leader who can: * Bridge **LLM + Agentic AI + RAG** with **FPGA/ASIC system architecture** * Drive **AI model optimization and deployment on FPGA** * Lead innovation in next-generation **AI + hardware integrated systems** **Qualifications:** ------------------- **Required** * Strong experience in **LLMs, agentic AI, or RAG systems** * Proven track record in **large-scale AI system architecture and deployment** * Solid programming skills in **Python/C++** and modern AI frameworks * Experience designing **distributed or production AI systems** * Strong system-level thinking across software and infrastructure **Preferred / Plus** * Experience with **FPGA, ASIC, or hardware acceleration platforms** * Familiarity with **FPGA development flows and toolchains** (e.g., synthesis, compilation, HLS, runtime) * Experience with **AI model optimization for hardware** (quantization, compilation, deployment) * Exposure to **EDA tools and semiconductor design workflows** * Background in **heterogeneous computing systems (CPU/GPU/FPGA)** **Job Type:** ------------- Regular **Shift:** ---------- Shift 1 (China) **Primary Location:** --------------------- Shanghai, China **Additional Locations:** ------------------------- **Posting Statement:** ---------------------- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.