Dsp Design Engineer

**Job Details:** ================ **Job Description:** -------------------- **About Altera** Altera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and software technologies that enable innovation across data centers, communications, automotive, aerospace & defense, and industrial markets. Our engineers tackle some of the most complex design challenges in the semiconductor industry, working at advanced technology nodes to build high-performance, power-efficient solutions used by customers worldwide. ​**About the Role** The DSP Design Engineer will oversee definition, design, verification, and documentation of state-of-the-art, AI-enhanced DSP IP for next generation FPGA families. Involves analyzing complex DSP topologies and develops parameterizable and efficient IP implementations.  Will determine microarchitecture design, logic design, RTL coding, and system simulation. Performs all aspects of the design flow from high level design to synthesis.  Oversees physical design place & route, and timing and power model generation.  You will be participating in planning and execution of design verification and silicon validation.  **If you have strong DSP/arithmetic design background, and a passion for cutting-edge silicon development, the Silicon Design Engineering group would love to speak with you!** **Responsibilities** * Design and implement high-performance DSP IP for next-generation FPGAs * Contribute to all phases of the design lifecycle including specification development, RTL design, timing closure, power optimization, and design signoff * Develop and optimize high-speed arithmetic circuits with a focus on performance, power, and area * Perform datapath synthesis, static timing analysis (STA), and timing closure for advanced process technologies * Collaborate closely with architecture, verification, physical design, and software teams to ensure robust and scalable solutions * Support formal verification, logic equivalence checking, and design validation activities * Participate in design reviews and provide technical leadership and mentorship within the team **Salary Range**  The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. **$118,900 - $169,000 USD** We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.  **Qualifications:** ------------------- **Minimum Qualifications** * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 4+ years of industry experience in digital hardware design, or a Master's degree with 2+ years of industry experience. * 2+ years of experience designing DSP datapaths, digital signal processing algorithms, or digital communication system hardware. * 2+ years of experience implementing high-speed arithmetic circuits and applying DSP fundamentals in digital hardware designs. * 2+ years of experience with RTL design using Verilog or SystemVerilog for FPGA and/or ASIC development. * 2+ years of experience with datapath synthesis, static timing analysis (STA), and timing closure techniques for high-performance digital designs. * 2+ years of experience using industry-standard EDA tools such as PrimeTime, Design Compiler, or equivalent synthesis and timing analysis tools. * 2+ years of experience with RTL simulation, timing constraints, and digital design verification methodologies. * 2+ years of experience working with ASIC or FPGA design flows, including synthesis, implementation, and verification. * 2+ years of experience with formal verification, logic equivalence checking, or related design validation methodologies. * Familiarity with place-and-route (PnR) tools and physical implementation concepts for digital IC design. * Strong understanding of the complete digital design lifecycle, including specification, RTL development, synthesis, verification, timing closure, and power optimization. * Strong analytical, debugging, and problem-solving skills with the ability to collaborate effectively in a cross-functional engineering environment. **Preferred Qualifications** * Strong background in arithmetic operations - fixed point, floating point, and tensor **Job Type:** ------------- Regular **Shift:** ---------- Shift 1 (United States of America) **Primary Location:** --------------------- San Jose, California, United States **Additional Locations:** ------------------------- **Posting Statement:** ---------------------- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.