Lead Product Engineer Soc Verification

**At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** ----------------------------------------------------------------------------------------------------------------- [Cadence Design Systems Inc.](http://www.cadence.com/) is looking for a motivated **Lead Product Engineer: SoC Verification** to work with us in Belo Horizonte, Brazil for **[Perspec](http://www.cadence.com/en_US/home/tools/system-design-and-verification/software-driven-verification/perspec-system-verifier.html)** Team. **[Perspec](http://Perspec,%20Cadence’s%20Portable%20Stimulus%20solution%20used%20by%20leading%20semiconductor%20companies%20to%20solve%20complex%20SoC%20and%20system-level%20verification%20challenges.%20%20This%20role%20sits%20at%20the%20intersection%20of%20verification%20methodology,%20system%20architecture,%20and%20EDA%20product%20engineering.%20You%20will%20work%20directly%20with%20advanced%20verification%20teams%20at%20major%20semiconductor%20companies%20to%20deploy%20Portable%20Stimulus%20%28PSS%29%20in%20real%20production%20environments%20and%20help%20drive%20the%20evolution%20of%20Perspec.%20%20The%20work%20spans%20formal%20languages,%20simulation,%20emulation,%20virtual%20platforms,%20firmware-driven%20verification,%20and%20post-silicon%20reuse,%20and%20increasingly%20involves%20AI-assisted%20verification%20workflows.)** is Cadence’s Portable Stimulus solution used by leading semiconductor companies to solve complex **SoC and system-level verification challenges**. This role sits at the intersection of **verification methodology, system architecture, and EDA product engineering**. You will work directly with advanced verification teams at major semiconductor companies to deploy **Portable Stimulus (PSS)** in real production environments and help drive the evolution of Perspec. The work spans **formal languages**, **simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse**, and increasingly involves **AI-assisted verification workflows**. Portable Stimulus is changing how system-level verification is done. In this role you will work on **real verification problems at scale**, interacting with some of the most advanced verification teams in the industry and helping shape how **hardware/software co-verification** is done across simulation, emulation, and silicon. If you enjoy **deep technical problem solving, modeling complex systems, and working close to both customers and EDA tool development**, this is a unique role. Cadence has been nominated as a [Great Place to Work](https://www.greatplacetowork.com/certified-company/1121485#:~:text=Company%20Culture%20at%20Cadence&text=91%25%20of%20employees%20at%20Cadence,a%20typical%20U.S.%2Dbased%20company.&text=Source%3A%20Great%20Place%20to%20Work,U.S.%20National%20Employee%20Engagement%20Study.) globally and in [Brazil](https://certificadas.gptw.com.br/certificada/cadence-design-systems-do-brasil), and is also a [Fortune 100 Best Companies to Work For](https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr/2022/fortune-and-great-place-to-work-name-cadence-to-the-2022-100.html). **Job Description:** * Work directly with semiconductor design and verification teams to deploy **Portable Stimulus methodologies** in complex SoC programs. * Help debug difficult generation and solver issues involving **constraints, resources, execution ordering, and scenario realization**. * Investigate real-world modeling challenges that arise in **large system-level PSS environments**. * Collaborate closely with **Cadence R&D** to diagnose tool issues, influence new features, and improve PSS standard * Help define and refine **methodologies for scalable system-level verification**. * Develop reference models, internal knowledge, and best practices used by both customers and Cadence field teams. * Support advanced system-level verification use cases including: * software-driven verification * device programming flows * reuse between simulation, emulation, and post-silicon * integration with virtual platforms and firmware environments * Contribute to emerging **AI-assisted verification flows** built around PSS models. **Requirements:** * Complete Bachelor's degree in Computer Science or related areas. * Experience in **SoC verification, validation, or verification methodology** * Strong hands-on experience with **SystemVerilog and UVM** or **embedded / bare metal environments** * Solid understanding of **constrained-random verification and system-level test generation** * Experience debugging complex verification environments * Strong programming or scripting skills (C/C++/Python or similar) * Ability to work directly with engineering teams to solve difficult technical problems **Nice to Have:** * Exposure to **Portable Stimulus (PSS)** or interest in learning it * Experience with **Perspec or other PSS tools** * Experience working with complex SoC subsystems and protocols such as **PCIe, DDR, networking**, or **ARM-based SoCs** * Experience with **embedded software programming and bare-metal environments** * Familiarity with **emulation, virtual platforms, or post-silicon validation** * Experience developing **verification methodology or reusable verification libraries** **Additional Job Details:** --------------------------- * Employment category: CLT. * Employment term: 40 hours/week. * Competitive benefits. * Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil. Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access [http://www.cadence.com](http://www.cadence.com/) **We’re doing work that matters. Help us solve what others can’t.** -------------------------------------------------------------------