Principal Design Engineer

**At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** ----------------------------------------------------------------------------------------------------------------- **Role Summary** We are looking for an experienced **Principal Analog Design Engineer** to drive the design and delivery of **high‑speed interface IPs**, with a strong emphasis on **Die‑to‑Die (D2D) interconnects based on the UCIe standard** and **advanced package technologies**. The role requires hands‑on ownership from **architecture through silicon bring‑up**, working closely with layout, verification, package, and system teams. **Key Responsibilities** * Architect, design, and deliver **high‑speed analog / mixed‑signal circuits** for Die‑to‑Die and chiplet‑based systems, including UCIe‑compliant interfaces. * Own analog blocks for **high‑speed interfaces** such as clocking, TX/RX front‑ends, termination schemes, biasing, and equalization support circuits. * Drive **architecture definition**, feasibility analysis, and design trade‑offs considering signal integrity, power, noise, and packaging parasitics. * Perform **schematic design, simulation, and optimization** across PVT corners using industry‑standard EDA tools. * Work closely with **advanced package teams** (2.5D / 3D, interposers, organic substrates) to co‑optimize circuit and package design. * Support **layout reviews**, parasitic extraction analysis, and post‑layout sign‑off for high‑speed performance. * Collaborate with **AMS verification**, digital, and system teams to enable full‑chip integration and validation. * Participate in **silicon bring‑up, debug, and characterization**, including correlation with simulation results. * Contribute to **design methodology, checklists, and best practices** for high‑speed analog and D2D designs. **Required Qualifications** * Bachelor’s or Master’s degree in **Electrical / Electronics Engineering** or related field. * **8+ years** of hands‑on experience in **analog / mixed‑signal IC design**. * Strong experience with **high‑speed interface design** (e.g., DDR, PCIe, SerDes, Die‑to‑Die links). * Solid understanding of **UCIe standard concepts**, D2D PHY requirements, and chiplet architectures. * Experience working with **advanced packaging technologies** and understanding package‑induced effects on high‑speed signaling. * Proficiency in **schematic‑level design, simulation, and debug** across PVT corners. * Strong fundamentals in **analog circuit theory**, signal integrity, noise analysis, and clocking. **Preferred / Nice‑to‑Have Skills** * Direct hands‑on experience with **UCIe PHY design or integration**. * Exposure to **AMS verification flows** and mixed‑signal simulation environments. * Experience with **post‑silicon debug** and correlation. * Knowledge of **power integrity, thermal considerations**, and package‑aware design flows. * Ability to mentor junior engineers and lead technical discussions. **What Success Looks Like** * Robust, scalable **UCIe / D2D analog IPs** meeting performance, power, and reliability targets. * Smooth collaboration across **design, verification, and packaging** teams. * Predictable execution aligned with **project milestones and KPIs / OKRs**. * Strong ownership mindset from **architecture to silicon**. **We’re doing work that matters. Help us solve what others can’t.** -------------------------------------------------------------------