Principal Soc Physical Implementation Sta Engineer

**Job Qualification:** *  Experienced Static Timing Analysis (STA) Lead with 12+ years of experience doing STA for SoCs and Blocks. * He/She should have experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes. * He/She will work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities **Key Responsibilities** * **Constraint Development:** Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes. * **Timing Signoff:** Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations. * **Violation Debugging:** Debug and resolve setup, hold, transition, and path-based violations (PBA). * **Optimization & ECO:** Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs). * **Cross-functional Collaboration:** Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models. * **Tool & Flow Automation:** Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation. * **Debugging timing issues from GLS** * **Drive a team of STA engineers.** [More information about NXP in India...](https://www.nxp.com/company/about-nxp/worldwide-locations/india:INDIA) #LI-7013