Senior Dft Engineer

**Design for Test (DFT) Engineer (Experienced)** We are looking for an experienced **DFT Engineer** with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage and quality silicon. **Key Responsibilities** ------------------------ * Define and implement **DFT architecture** including scan, MBIST, and boundary scan. * Perform **scan insertion**, chain stitching, and compression techniques. * Generate and analyze **ATPG patterns** to achieve high fault coverage. * Debug and resolve **DFT-related issues** across design and silicon stages. * Work closely with **RTL, Physical Design, and STA teams** for smooth integration. * Support **pattern validation, gate-level simulations, and silicon bring-up**. * Ensure compliance with **DFT and testability requirements**. [More information about NXP in India...](https://www.nxp.com/company/about-nxp/worldwide-locations/india:INDIA) #LI-2734