Design Verification Engineer 2 – Cpu Subsystem
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Server Firmware Architect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Confidential Computing Software Architect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Datacenter System Software Architect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Linux Kernel Architect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Principal Design Verification Engineer – Cpu Core Frontend
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Principal Design Verification Engineer – Cpu Core Hardware Prefetch
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Principal Design Verification Engineer – Cpu Subsystem Power Management
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Principal Design Verification Engineer – Cpu Core Lsu
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Interconnect Design Engineer
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Platform Technologies Language & Frontend Design Engineer
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Senior Staff Design Verification Engineer – Coherent Interconnect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Director of Licensing
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Staff Rtl Design Engineer - Cpu Ls Pf Mmu
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Intern - Design Verification Infrastructure Engineer - Platform
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Staff Design Verification Engineer – Coherent Interconnect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Principal Design Verification Engineer – High Performance Cpu Subsystem
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Staff Verification Engineer
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Senior PM
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Executive Business Partner Executive Assistant to the CTO & EVP Engineering
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Soc Architect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Core Performance Architect
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Cpu Power-Management Design Engineer
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R
Workload Performance Model Lead
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****About SiFive**** -------------------- _As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of R